View AS6C1016-55BIN_7557366.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 0 revision history revision description issue date rev. 1. 0 initial issue nov . 19 .200 8 rev. 1.1 revised features & ordering information lead free and green p ackage available to g reen p ackage available added packing type in ordering information deleted t solder in absolute maximun ratings revised package outline dimension in page 11 revised v dr to 1.5v may . 6 .20 10 rev. 1.2 revised ordering information in page 12 aug . 30 .20 10 rev. 1.3 revised typo in product family page 1 oct . 4 .20 10 rev. 1.4 deleted e grade aug . 9 .20 11
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 1 features ? fast access time : 55 ns ? low power consumption: operating current : 20 ma ( typ . ) standby current : 2 ? a ( typ . ) ? single 2.7 v ~ 5 . 5 v power supply ? all o utputs ttl compatible ? fully static operation ? tr i - state output ? data byte control : lb# ( dq0 ~ dq7 ) ub# ( dq8 ~ dq15 ) ? data retention voltage : 1.5 v ( min .) ? g reen p ackage available ? package : 44 - pin 4 00 mil tsop - ii 4 8 - ball 6mm x 8mm tfbga general description the as6c1016 is a 1 , 0 48 , 576 - bit low power cmos static random access memory organized as 65 , 536 words by 16 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the as6c1016 is well designed for low power application, and particularly well suited for bat tery back - up nonvolatile memory application. the as6c1016 operates from a single power supply of 2.7 v ~ 5.5 v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby( i sb1, typ.) operating( icc,typ.) as6c1016 (i) - 4 0 ~ 85 functional block diagram pin description symbol description a0 - a1 5 address inputs dq0 C cc power supply v ss ground control circuit ce # we # oe # decoder 64 kx 16 memory array column i / o a 0 - a 15 vcc vss dq 8 - dq 15 upper byte dq 0 - dq 7 lower byte i / o data circuit lb # ub #
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 2 pin configuration absolute maximun ratings * parameter symbol rating unit voltage on v cc relative to v ss v t 1 - 0.5 to 6.5 v voltage on any other pin relative to v ss v t 2 - 0.5 to v cc +0.5 v operating temperature t a - 4 0 to 85 (i grade) stg - 65 to 150 d 1 w dc output current i out 50 ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not imp lied. exposure to the absolute maximum rating conditions for extended period may affect device reliability. a s 6 c 1 0 1 6 a 1 a 2 a 3 a 4 d q 1 5 d q 0 d q 1 d q 2 v c c v s s n c a 1 5 d q 1 4 d q 1 2 d q 1 3 d q 1 1 v s s v c c d q 1 0 d q 9 d q 3 d q 4 t s o p i i 2 8 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 7 1 6 1 5 2 0 1 9 1 8 2 2 2 3 2 4 2 5 2 6 2 7 2 1 a 1 4 a 0 d q 6 d q 7 a 5 a 6 a 7 a 8 a 9 d q 5 d q 8 a 1 3 a 1 2 n c a 1 0 n c 3 4 2 9 3 0 3 1 3 2 3 3 4 4 3 9 4 0 4 1 4 2 4 3 3 5 3 6 3 7 3 8 a 1 1 c e # w e # l b # u b # o e # tfbga nc a 3 a 10 a 9 a 11 a 0 a 14 a 8 nc we # dq 9 dq 14 dq 15 nc vss nc a 13 dq 8 vcc vcc dq 7 a 15 vss ce # lb # dq 6 dq 2 dq 0 a 2 oe # a 1 a 6 a 5 a 4 ub # 1 2 3 4 5 6 h g c d e f a b a 12 nc nc a 7 nc dq 10 dq 11 dq 12 dq 13 dq 5 dq 4 dq 3 dq 1
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 3 truth table mode ce# oe# we# lb# ub# i/o operation supply current dq0 - dq7 dq8 - dq15 standby h x x x x x x h x h high C C C C sb1 output disable l l h h h h l x x l high C C C C cc ,i cc1 read l l l l l l h h h l h l h l l d out high C out high C out d out i cc ,i cc1 write l l l x x x l l l l h l h l l d in high C in high C in d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 2.7 3.0 5.5 v input high voltage v ih *1 2.4 - v cc +0. 3 v input low voltage v il *2 - 0. 2 - 0.6 v input leakage current i li v cc R in R ss - 1 - 1 a output leakage c urrent i lo v cc R out R ss , output disabled - 1 - 1 a output high voltage v oh i oh = - 1ma 2. 4 2.7 - v output low voltage v ol i ol = 2 ma - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il , i i/o = 0ma o ther pins at v il or v ih - 5 5 - 20 60 ma i cc1 cycle time = 1 s ce# = 0.2v , i i/o = 0ma o ther pins at 0.2v or v cc - 0.2v - 4 10 ma standby power supply current i sb1 ce# R cc - 0.2v other s at 0.2v or v cc - 0.2v ll/lli - 2 50 a notes: 1. v ih (max) = v cc + 3.0 v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0 v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4 . typical values are included for reference only and are not guaranteed or tested. typical value s are measured at v cc = v cc (typ.) and t a = 25 5. this parameter is measured at v cc = 3.0v
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 4 capacitance (t a = 25 parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0 .2 v to v cc - 0.2 v input rise and fall times 3 ns input and output timing reference levels 1.5v output load c l = 3 0pf + 1ttl , i oh /i ol = - 2 ma/ 4 ma ac electrical characteristics (1) read cycle parameter sym . as6c1016 - 55 unit min. max. read cycle time t rc 55 - ns address access time t aa - 55 ns chip enable access time t ace - 55 ns output enable access time t oe - 30 ns chip enable to output in low - z t clz * 10 - ns output enable to output in low - z t olz * 5 - ns chip disable to output in high - z t chz * - 20 ns output disable to output in high - z t ohz * - 20 ns output hold from address change t oh 10 - ns lb#, ub# a c cess time t ba - 55 ns lb#, ub# to high - z output t bhz * - 25 n s lb#, ub# to low - z output t blz * 10 - ns (2) write cycle parameter sym . as6c1016 - 55 unit min. max. write cycle time t wc 55 - ns address valid to end of write t aw 50 - ns chip enable to end of write t cw 50 - ns address set - up time t as 0 - ns write pulse width t wp 45 - ns write recovery time t wr 0 - ns data to write time overlap t dw 25 - ns data hold from end of write time t dh 0 - ns output active from end of write t ow * 5 - ns write to output in high - z t whz * - 2 0 ns lb#, ub# valid to end of write t b w 5 0 - ns *these parameters are guaranteed by device characterization, but not production tested.
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 5 t iming waveforms read cycle 1 (address controlled) (1,2) read cycle 2 ( ce# and oe# controlled) (1,3,4,5) notes : 1. we# is high for read cycle. 2.device is continuously selected oe# = low , ce# = low, lb# or ub# = low . 3.address must be valid prior to or coincident with ce# = low, lb# or ub# = low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz, t olz , t chz, t bhz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz . dout data valid t oh t aa address t rc previous data valid dout data valid high - z high - z t clz t olz t chz t ohz t oh oe # t oe lb #, ub # t bhz t ace ce # t aa address t rc t ba t blz
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 6 write cycle 1 ( we# controlled) (1,2,3,5,6) write cycle 2 ( ce# c ontrolled) (1,2,5,6) dout din data valid t d w t d h ( 4 ) high - z t whz we # t wp t cw t wr t as ( 4 ) t ow lb #, ub # ce # t aw address t wc t bw dout din data valid t d w t d h ( 4 ) high - z t whz we # lb #, ub # t cw ce # address t wr t as t aw t wc t wp t bw
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 7 write cycle 3 ( lb# , ub# controlled) (1,2,5 ,6 ) notes : 1. we#,ce#, lb#, ub# must be high during all address transitions. 2.a write occurs during the overlap of a low ce#, low we#, lb# or ub# = low. 3.during a we# controlled write cycle with oe# low , t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the output state, and input signals must not be applied. 5.if the ce#, lb#, ub# low transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. dout din data valid t d w t d h ( 4 ) high - z t whz we # lb #, ub # t cw ce # address t wr t as t aw t wc t wp t bw
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 8 data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# R v cc - 0.2v 1.5 - 5.5 v data retention current i dr v cc = 1.5 v ce# R v cc - 0.2v o ther s at 0.2v or v cc - 0.2v l l /lli - 0.5 20 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform low vcc data retention waveform (1) ( ce# controlled) low vcc data retention waveform ( 2 ) ( lb# , ub# controlled) vcc ce # v dr ? 1 . 5 v ce # ? v cc - 0 . 2 v v cc ( min .) v ih t r t cdr v ih v cc ( min .) vcc lb #, ub # v dr ? 1 . 5 v lb #, ub # ? v cc - 0 . 2 v v cc ( min .) v ih t r t cdr v ih v cc ( min .)
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 9 package outline dimension 44 - pin 400mil tsop - symbols dimensions in millmeters dimensions in mils min. nom. max. min. nom. max. a - - 1.20 - - 47 .2 a1 0.05 0.10 0.15 2.0 3.9 5.9 a2 0.95 1.00 1.05 37 .4 39 .4 41 .3 b 0.30 - 0.45 11.8 - 17.7 c 0.12 - 0.21 4 . 7 - 8 . 3 d 18. 212 18.415 18. 618 7 17 725 7 33 e 11. 506 11. 760 1 2.014 4 53 46 3 47 3 e1 9 . 957 10.1 6 0 10. 363 39 2 400 40 8 e - 0.800 - - 31 . 5 - l 0.40 0.50 0.60 15 . 7 19.7 23 . 6 z d - 0.805 - - 31 . 7 - y - - 0.076 - - 3 0 o 3 o 6 o 0 o 3 o 6 o
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 10 48 - ball 6mm 8mm tfbga package outline dimension
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 11 ordering information alliance organization vcc range package operating temp speed ns as6c1016 - 55zin 64k x 16 2.7v C 5.5v 44pin tsop ii industrial ~ - 40c - 85c 55 as6c1016 - 55bin 64k x 16 2.7v C 5.5v 48ball tfbga industrial - - 40c - 85c 55 part numbering system as6c 1016 - 55 x x n low power sram prefix device number 10 = 1m 16 = x16 access time package options: t = 44 pin tsop ii b = 48 ball tfbga temperature range: i = industrial ( - 40c to +85c) n = lead free rohs compliant part
as6c1016 64 k x 16 bit low power cmos sram alliance memory, inc. rev. 1.4 12 this page is left blank intentionally.

▲Up To Search▲

Price & Availability of AS6C1016-55BIN

	To Download AS6C1016-55BIN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .